One of the most magical parts of an RTOS is when the CPU suddenly stops running one function and starts running another \u2014 as if by sleight of hand. In MicrOS<\/strong>, this magic is powered by the PendSV exception<\/strong> and carefully constructed stack frames<\/strong> for each thread.<\/p>\n\n\n\n This post goes under the hood and shows how threads are \u201cbootstrapped\u201d and how PendSV safely swaps them, cycle after cycle.<\/p>\n\n\n\n On Cortex-M, any exception (IRQ, SysTick, PendSV) triggers automatic stacking<\/strong>. The hardware pushes these 8 words onto the current stack pointer (PSP if in thread mode, MSP if in handler mode):<\/p>\n\n\n\n This is called the exception stack frame<\/strong>. When the exception returns, the CPU automatically pops<\/strong> these values back, restoring execution exactly where it left off.<\/p>\n\n\n\n When MicrOS creates a thread, it doesn\u2019t just give it a stack. It pre-loads<\/strong> the stack with a fake exception frame so that when the scheduler runs it for the first time, the CPU \u201creturns\u201d directly into the task function.<\/p>\n\n\n\n For example, in The very first exception return the CPU executes lands inside your task function, with the argument already loaded into R0.<\/p>\n\n\n\n Now, how do we swap between two such prepared contexts? Enter PendSV_Handler<\/strong>.<\/p>\n\n\n\n MicrOS\u2019s PendSV does:<\/p>\n\n\n\n Let\u2019s see the stack layouts for Thread A<\/strong> (outgoing) and Thread B<\/strong> (incoming):<\/p>\n\n\n\n PendSV saves A\u2019s R4\u2013R11, calls the scheduler, loads B\u2019s PSP, restores B\u2019s R4\u2013R11, and returns. Hardware pops the rest of B\u2019s frame \u2014 and suddenly Thread B is running<\/strong>.<\/p>\n\n\n\n Two registers are especially important:<\/p>\n\n\n\n A mismatch here is the #1 reason for \u201clockup\u201d errors in QEMU.<\/p>\n\n\n\n The beauty of Cortex-M is that the CPU does half the work. Hardware saves and restores volatile registers automatically; the RTOS only needs to manage the callee-saved ones ( This is why MicrOS can implement multitasking with just a few dozen lines of C and a small naked handler.<\/p>\n\n\n\n In MicrOS today:<\/p>\n\n\n\n Understanding this mechanism makes context switching less of a black box and more of a predictable, elegant process.<\/p>\n\n\n\n \ud83d\udc49 Next post: wiring SysTick + PendSV<\/strong> together for preemptive round-robin scheduling in MicrOS.<\/p>\n","protected":false},"excerpt":{"rendered":" One of the most magical parts of an RTOS is when the CPU suddenly stops running one function and starts running another \u2014 as if by sleight of hand. In MicrOS, this magic is powered by the PendSV exception and carefully constructed stack frames for each thread. This post goes under the hood and shows […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[8,6],"tags":[],"class_list":["post-141","post","type-post","status-publish","format-standard","hentry","category-context-switch","category-development"],"blocksy_meta":[],"_links":{"self":[{"href":"https:\/\/microsproject.dev\/index.php\/wp-json\/wp\/v2\/posts\/141","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/microsproject.dev\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/microsproject.dev\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/microsproject.dev\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/microsproject.dev\/index.php\/wp-json\/wp\/v2\/comments?post=141"}],"version-history":[{"count":1,"href":"https:\/\/microsproject.dev\/index.php\/wp-json\/wp\/v2\/posts\/141\/revisions"}],"predecessor-version":[{"id":142,"href":"https:\/\/microsproject.dev\/index.php\/wp-json\/wp\/v2\/posts\/141\/revisions\/142"}],"wp:attachment":[{"href":"https:\/\/microsproject.dev\/index.php\/wp-json\/wp\/v2\/media?parent=141"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/microsproject.dev\/index.php\/wp-json\/wp\/v2\/categories?post=141"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/microsproject.dev\/index.php\/wp-json\/wp\/v2\/tags?post=141"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
\n\n\n\nHardware\u2019s Role: The Automatic Exception Frame<\/h2>\n\n\n\n
Offset<\/th> Register<\/th> Notes<\/th><\/tr><\/thead> 0x00<\/td> R0<\/td> Argument register<\/td><\/tr> 0x04<\/td> R1<\/td> Volatile<\/td><\/tr> 0x08<\/td> R2<\/td> Volatile<\/td><\/tr> 0x0C<\/td> R3<\/td> Volatile<\/td><\/tr> 0x10<\/td> R12<\/td> Scratch<\/td><\/tr> 0x14<\/td> LR<\/td> Link register<\/td><\/tr> 0x18<\/td> PC<\/td> Resume address<\/td><\/tr> 0x1C<\/td> xPSR<\/td> Program status word (must have Thumb bit set)<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n
\n\n\n\nCreating a Task: Building the Initial Frame<\/h2>\n\n\n\n
micros_thread_create()<\/code>:<\/p>\n\n\n\nHigh memory\n+--------------------+\n| free stack |\n| ... |\n+--------------------+\n| R11 (dummy) |\n| R10 |\n| R9 |\n| R8 |\n| R7 |\n| R6 |\n| R5 |\n| R4 | <- SW-saved area\n+--------------------+\n| R0 = arg |\n| R1 (dummy) |\n| R2 (dummy) |\n| R3 (dummy) |\n| R12 (dummy) |\n| LR = 0xFFFFFFFD | <- tells CPU: return to thread, use PSP\n| PC = entry() | <- task entry point\n| xPSR = 0x01000000 | <- Thumb bit set\n+--------------------+\nLow memory\n<\/code><\/pre>\n\n\n\n
\n\n\n\nSwitching Context in PendSV<\/h2>\n\n\n\n
\n
\n
R0\u2013R3, R12, LR, PC, xPSR<\/code>.<\/li>\n\n\n\nR4\u2013R11<\/code> onto the PSP.<\/li>\n\n\n\n\n
micros_context_switch(old_sp)<\/code>.<\/li>\n\n\n\nthread->sp = old_sp<\/code>) and chooses the next runnable thread.<\/li>\n\n\n\n\n
R4\u2013R11<\/code> from the new thread\u2019s stack.<\/li>\n\n\n\n\n
BX lr<\/code> exits PendSV.<\/li>\n\n\n\nR0\u2013R3, R12, LR, PC, xPSR<\/code>) from the PSP.<\/li>\n\n\n\n
\n\n\n\nVisualizing the Context Switch<\/h2>\n\n\n\n
Thread A stack before switch (PSP):\n +--------------------+\n | R11 |\n | R10 |\n | ... |\n | R4 | <- saved by PendSV\n +--------------------+\n | R0 |\n | R1 |\n | R2 |\n | R3 |\n | R12 |\n | LR |\n | PC |\n | xPSR | <- stacked by HW\n +--------------------+\n PSP -> bottom\n\nThread B stack ready to run (PSP):\n +--------------------+\n | R11 |\n | R10 |\n | ... |\n | R4 | <- prebuilt by create()\n +--------------------+\n | R0 = arg |\n | R1..R3 dummy |\n | R12 dummy |\n | LR = 0xFFFFFFFD |\n | PC = entry() |\n | xPSR = 0x01000000 |\n +--------------------+\n PSP -> bottom\n<\/code><\/pre>\n\n\n\n
\n\n\n\nThe Subtleties: LR and PSP<\/h2>\n\n\n\n
\n
\n
0xFFFFFFFD<\/code> means: return to Thread mode, use PSP, pop registers<\/em>.<\/li>\n\n\n\n\n
micros_context_switch()<\/code>.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\n
\n\n\n\nWhy This Works<\/h2>\n\n\n\n
R4\u2013R11<\/code>) and PSP bookkeeping.<\/p>\n\n\n\n
\n\n\n\nTakeaway<\/h2>\n\n\n\n
\n
\n\n\n\n